{"id":1932,"date":"2015-12-01T22:56:31","date_gmt":"2015-12-02T04:56:31","guid":{"rendered":"http:\/\/dev.iachieved.it\/iachievedit\/?p=1932"},"modified":"2022-11-21T11:04:08","modified_gmt":"2022-11-21T17:04:08","slug":"gpio-chip-selects-with-the-beaglebone","status":"publish","type":"post","link":"https:\/\/dev.iachieved.it\/iachievedit\/gpio-chip-selects-with-the-beaglebone\/","title":{"rendered":"GPIO Chip Selects with the BeagleBone"},"content":{"rendered":"

In my previous post<\/a> I made mention that I could not use GPIO-based SPI<\/a> chip selects on the BeagleBone Black<\/a> with<\/i> the default McSPI<\/a> driver (what you are using if you’re opening \/dev\/spidev<\/code>. The exact quote I had run across (much to my chagrin at the time) was<\/p>\n

\nIncidentally, the spi-omap2-mcspi.c driver does not support a GPIO as a chip select.\n<\/p><\/blockquote>\n

Well, fortunately, a little persistence paid off (I confess, I can be stubborn at times), and I found this patch<\/a> from Michael Welling<\/a> that adds GPIO chip select support to the spi-omap2-mcspi.c<\/code> driver.<\/p>\n

As I mentioned in the article<\/a> on using the 4-slot mikroBUS cape<\/a> I was using a workaround to lower the chip select by hand. With Linux 4.3 and one additional patch<\/i> you no longer need it. I’ve included everything in the BBB-420mA<\/a> repository on the linux-4.3<\/code> branch, but wanted to share some additional tips for those looking to work with the cs-gpios<\/code> tag in DTS files.<\/p>\n

Declare your Pins<\/h3>\n

The snippet below cannot be taken out of context from the larger DTS overlay<\/a>, but illustrates that we put our GPIO chip select pin in the same group as the rest of the SPI1 pins.<\/p>\n

\n    bb_spi1_pins: pinmux_bb_spi1_pins {\n    pinctrl-single,pins = <\n      0x190 0x33    \/* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 *\/\n      0x194 0x33    \/* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 *\/\n      0x198 0x13    \/* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 *\/\n      0x19c 0x13    \/* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 *\/\n      0x164 0x12    \/* eCAP0_in_PWM0_out.spi1_cs1 OUTPUT_PULLUP | MODE2 *\/\n      0x098 0x17    \/* P8 10 gpio2_4.spi1_cs2 OUTPUT_PULLUP | MODE7 *\/\n      >;\n      };\n<\/pre>\n
In particular the “magic” 0x098 0x17<\/code> refers to P8.10 on the Black (and actually the 0x098<\/code> refers to the pin and the 0x17<\/code> refers to the settings, which in this case we want OUTPUT_PULLUP and MODE7), which is gpio68 in \/sys\/class\/gpio<\/code>.  Another name for it, which we’ll see below, is <&gpio2 4 0><\/code>.  So<\/i> many ways are referring to the same thing.  No wonder it gets confusing.<\/p>\n
Next, let’s revisit our DTS for SPI1 on the Black:<\/p>\n
\n  fragment@1 {\n    target = <&spi1>;   \/* spi1 is numbered correctly *\/\n    __overlay__ {\n      status = \"okay\";\n      pinctrl-names = \"default\";\n      pinctrl-0 = <&bb_spi1_pins>;\n\n#address-cells = <1>;\n#size-cells = <0>;\n\n      cs-gpios = <0>, <0>, <&gpio2 4 0>;\n\n      spi1@0 {\n#address-cells = <1>;\n#size-cells = <0>;\n    compatible = \"spidev\";\n    reg = <0>;\n    spi-max-frequency = <16000000>;\n    spi-cpol;\n    spi-cpha;          \n      };\n\n      spi1@1 {\n#address-cells = <1>;\n#size-cells = <0>;\n    compatible = \"spidev\";\n    reg = <1>;\n    spi-max-frequency = <16000000>;\n    spi-cpol;\n    spi-cpha;\n      };\n\n      spi1@2 {\n#address-cells = <1>;\n#size-cells = <0>;\n    compatible = \"spidev\";\n    reg = <2>;\n    spi-max-frequency = <16000000>;\n    spi-cpol;\n    spi-cpha;\n      };\n    };\n  };\n<\/pre>\n
The SPI bus documentation<\/a> is a little<\/i> unclear, but the format for the cs-gpios<\/code> tag is:<\/p>\n
\ncs-gpios = <\/b> <<\/b>GPIO<\/i>><\/b>|<0><\/b>,<\/b> <<\/b>GPIO<\/i>><\/b>|<0><\/b>,<\/b> ...,<\/b> <<\/b>GPIO<\/i>><\/b>|<0><\/b>;<\/b>\n<\/pre>\n
where<\/p>\n